In computing, interleaved memory is a design which compensates for the comparatively sluggish pace of dynamic random-entry memory (DRAM) or core memory, by spreading memory addresses evenly across memory banks. That approach, contiguous memory reads and writes use each memory financial institution in turn, resulting in increased memory throughput as a consequence of decreased waiting for memory banks to turn out to be prepared for the operations. It is completely different from multi-channel memory architectures, primarily as interleaved memory doesn't add extra channels between the main memory and the memory controller. Nevertheless, channel interleaving is also attainable, for example in freescale i.MX6 processors, which permit interleaving to be finished between two channels. With interleaved memory, memory addresses are allocated to every memory bank in turn. For example, in an interleaved system with two memory banks (assuming word-addressable memory), if logical deal with 32 belongs to bank 0, then logical address 33 would belong to financial institution 1, logical handle 34 would belong to bank 0, and so forth. An interleaved memory is alleged to be n-method interleaved when there are n banks and memory location i resides in financial institution i mod n.

Interleaved memory leads to contiguous reads (that are common each in multimedia and execution of packages) and contiguous writes (which are used continuously when filling storage or communication buffers) truly utilizing every memory financial institution in flip, instead of using the same one repeatedly. This leads to significantly greater memory throughput as every financial institution has a minimal waiting time between reads and writes. Most important memory (random-entry Memory Wave Protocol, RAM) is often composed of a set of DRAM memory chips, where plenty of chips may be grouped collectively to kind a memory financial institution. It is then attainable, with a memory controller that supports interleaving, to put out these memory banks in order that the memory banks can be interleaved. Information in DRAM is saved in items of pages. Every DRAM financial institution has a row buffer that serves as a cache for accessing any web page in the bank. Earlier than a page within the DRAM financial institution is learn, it is first loaded into the row-buffer.
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If the page is instantly learn from the row-buffer (or a row-buffer hit), it has the shortest memory access latency in one memory cycle. If it is a row buffer miss, which can be referred to as a row-buffer conflict, it's slower as a result of the new web page needs to be loaded into the row-buffer before it is learn. Row-buffer misses happen as access requests on totally different memory pages in the same financial institution are serviced. A row-buffer conflict incurs a substantial delay for a memory entry. In contrast, memory accesses to different banks can proceed in parallel with a excessive throughput. The problem of row-buffer conflicts has been nicely studied with an effective answer. The dimensions of a row-buffer is often the size of a memory page managed by the operating system. Row-buffer conflicts or misses come from a sequence of accesses to distinction pages in the identical memory financial institution. The permutation-primarily based interleaved memory technique solved the problem with a trivial microarchitecture value.

Sun Microsystems adopted this the permutation interleaving technique shortly of their products. This patent-free technique will be discovered in many business microprocessors, corresponding to AMD, Intel and NVIDIA, for embedded programs, laptops, desktops, and enterprise servers. In conventional (flat) layouts, memory banks can be allotted a contiguous block of memory addresses, which is quite simple for the memory controller and provides equal efficiency in fully random entry scenarios, when compared to efficiency levels achieved through interleaving. Nevertheless, in actuality memory reads are rarely random due to locality of reference, and optimizing for shut together entry offers far better performance in interleaved layouts. The best way memory is addressed has no effect on the access time for memory areas that are already cached, having an impact only on memory places which need to be retrieved from DRAM. Zhao Zhang, Zhichun Zhu, and Xiaodong Zhang (2000). A Permutation-based mostly Web page Interleaving Scheme to reduce Row-buffer Conflicts and Exploit Knowledge Locality. Division of Laptop Science and Engineering, Faculty of Engineering, Ohio State University. Mark Smotherman (July 2010). "IBM Stretch (7030) - Aggressive Uniprocessor Parallelism".